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A low-power switched-current CDMA matched filter employing MOS linear matching cell with on-chip A/D converter |
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| Authors: | Toshihiko Yamasaki [Author Vitae] Tomoyuki Nakayama [Author Vitae] [Author Vitae] |
| Affiliation: | a Department of Information and Communication Engineering, Graduate School of Information Science and Technology, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656, Japan b Department of Frontier Informatics, Graduate School of Frontier Sciences, The University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656, Japan |
| Abstract: | A low-power switched-current matched filter (MF) for code-division multiple-access (CDMA) systems has been developed. The front-end voltage-to-current (V/I) converter has been eliminated by merging the function into each matching cell utilizing the MOS linear I-V characteristics. A low-power analog-to-digital (A/D) converter has also been developed to establish smooth interfacing to digital back-end processing for a delayed locked loop (DLL) and a RAKE receiver. A proof-of-concept chip was fabricated in a 0.35-μm standard CMOS technology with a measured power consumption of 1.65 mW at 11 Mchip/s with 2-V power supply including the A/D converter. |
| Keywords: | Matched filter CDMA Analog Switched-current |
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