| 多通道NAND闪存控制器的硬件实现 |
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| 引用本文： | 陈宏铭,程玉华.多通道NAND闪存控制器的硬件实现[J].中国集成电路,2011,20(9):40-47. |
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| 作者姓名： | 陈宏铭 程玉华 |
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| 作者单位： | 北京大学上海微电子研究院,上海,201203 |
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| 摘 要： | 本文提出了在一款片上系统(SOC)芯片设计中的多通道NAND闪存控制器实现方案。在对NAND闪存控制器的结构和实现方法的研究上,闪存控制器利用带两个16K字节缓冲器的高效率缓冲管理控制器来管理4个通道,每个通道可以连接4片闪存芯片。控制器内嵌16比特BCH纠错模块,支持AMBAAHB总线与MLC闪存。文中还介绍了行地址计算与快闪存储器存储单元的初始化。结果分析里给出了控制器的仿真波形、功耗分析和综合结果。在一个存储组与一个通道的配置条件下,控制器的实现只需要71K逻辑门。
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| 关 键 词： | NAND闪存 BCH纠错 AHB总线 缓冲 |
The Hardware Implementation of Multi-Channel NAND Flash Controller |
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| CHEN Hong-ming,CHENG Yu-hua ,Peking University,Shanghai,.The Hardware Implementation of Multi-Channel NAND Flash Controller[J].China Integrated Circuit,2011,20(9):40-47. |
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| Authors: | CHEN Hong-ming CHENG Yu-hua Peking University Shanghai |
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| Affiliation: | CHEN Hong-ming,CHENG Yu-hua (Shanghai Research Institute of Microelectronics (SHRIME),Peking University,Shanghai,201203) |
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| Abstract: | In this paper, we proposed a solution to implement a multi-channel NAND flash controller for SoC design. There is a high efficiency buffer management controller which is applied to manage 4 channels through two 16K byte SRAMs inside the NAND flash controller. 4 flash chips can be connected in each channel by using chip enable pin. There is a 16bit BCH error correction module inside the controller according to ECC algorithm. The proposed controller support AMBA AHB interface and MLC NAND flash. We also intro... |
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| Keywords: | NAND Flash BCH ECC AHB Buffer |
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