| 高性能通用DSP译码器设计 |
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| 引用本文： | 孙立宏,付秀兰,宋何娟.高性能通用DSP译码器设计[J].中国集成电路,2014(6):29-31. |
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| 作者姓名： | 孙立宏 付秀兰 宋何娟 |
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| 作者单位： | 中国电子科技集团公司第三十八研究所集成电路设计中心,安徽合肥230031 |
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| 摘 要： | 高性能通用数字信号处理器译码器是连接指令集与运算单元的关键部件。它的输入数据是指令行的二进制机器码,输出是运算部件的所有控制信息、数据通道的所有控制信号和数据等。本文针对高性能通用数字信号处理器的特点,详述了译码器的硬件RTL设计实现过程,并给出了仿真实验结果。
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| 关 键 词： | 数字信号处理器 译码器 RTL |
The Design of High-performance Digital Signal Processor Decoder |
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| SUN Li-hong,FU Xiu-lan,SONG He-juan.The Design of High-performance Digital Signal Processor Decoder[J].China Integrated Circuit,2014(6):29-31. |
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| Authors: | SUN Li-hong FU Xiu-lan SONG He-juan |
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| Affiliation: | (IC Design Center, No.38 Institute, China Electronics Technology Group Corporation, Hefei 230031, China) |
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| Abstract: | High-performance digital signal processor decoder is a key component which connects the instruction set with arithmetic logic units. In the decoder, the input data is the binary machine code of the instruction line, meanwhile, the output data is the control signals of computation components and data channels. According to the characteristics of high-performance DSP, this paper introduces the hardware RTL design process of the decoder in detail, and produces the results of simulation in the end. |
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| Keywords: | DSP Decoder RTL |
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