| 基于CPLD的ADSP21060与SDRAM接口设计 |
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| 引用本文： | 张华春,雷宏,孙长瑜.基于CPLD的ADSP21060与SDRAM接口设计[J].信号处理,2002,18(6):551-555. |
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| 作者姓名： | 张华春 雷宏 孙长瑜 |
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| 作者单位： | 1. 中国科学院电子学研究所,北京,100080
2. 中国科学院声学研究所,北京,100080 |
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| 摘 要： | ADSP21060是广泛应用于实时信号处理系统中的数字信号处理器。对于图像信号的处理,数字信号处理系统要求具有大容量的存储器。SDRAM具有高速和大容量的特点,但是ADSP21060其接口与SDRAM不兼容。在ADSP21060的外存储器扩展中,本文基下CPLD设计力法,给出了所实现的ADSP21060与SDRAM之间的接口电路设计。
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| 关 键 词： | 数字信号处理器 SDRAM CPLD设计 |
| 修稿时间： | 2002年5月31日 |
Interface Design between ADSP21060 and SDRAM Based on CPLD |
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| Zhang Huachun Lei Hong Sun Changyu.Interface Design between ADSP21060 and SDRAM Based on CPLD[J].Signal Processing,2002,18(6):551-555. |
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| Authors: | Zhang Huachun Lei Hong Sun Changyu |
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| Abstract: | ADSP21060 is one of the digital signal processors that are widely used in many real-time signal processing systems. In image signal processing, the system demands large and fast memories. SDRAM possesses high speed and larger capacities, but the ADSP21060 cannot directly interface with SDRAM due to the difference between interface control signals. Based on complex programmable logic device (CPLD) design method, a hardware interface design between ADSP21060 and SDRAM for high-speed data access is proposed. Used in ADSP21060 off-chip memory extension, the interface circuit realizes large capacities data access. |
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| Keywords: | Digital signal processing SDRAM CPLD design |
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