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高效可配置浮点FFT处理器设计
引用本文:桑红石,高伟.高效可配置浮点FFT处理器设计[J].微电子学与计算机,2012,29(4):36-40.
作者姓名:桑红石  高伟
作者单位:华中科技大学图像识别与人工智能研究所多谱信息处理技术国家级重点实验室,湖北武汉,430074
摘    要:为了克服高精度浮点FFT处理器具有较大资源开销的设计瓶颈,采用基于单口存储器的FIFO构建共享蝶形结构的R2/22SDF流水可配置结构.采用适合浮点设计的基2/22算法实现流水结构,不仅有利于可配置电路的实现,还能够有效减少复数乘法次数,提高复数乘法器的计算效率.采用双倍数据位宽的单口存储器实现FIFO存储器,有效避免了双口存储器面积和功耗较大的问题.改进的蝶形共享结构实现两级蝶形的合并,解决了单路径延迟反馈流水线结构蝶形单元利用率低的问题.与传统流水线结构FFT处理器设计相比,有效降低了浮点设计中的资源开销,提高了计算单元的利用效率.

关 键 词:快速傅里叶变换  可配置浮点设计  共享蝶形  单路径流水结构

An Efficient Architecture Design of Reconfigurable Float-point FFT Processor
SANG Hong-shi,GAO Wei.An Efficient Architecture Design of Reconfigurable Float-point FFT Processor[J].Microelectronics & Computer,2012,29(4):36-40.
Authors:SANG Hong-shi  GAO Wei
Affiliation:(National Key Laboratory of Science and Technology on Multi-spectral Information Processing, Institute for Pattern Recognition and Artificial Intelligence,Huazhong University of Science and Technology,Wuhan 430074,China)
Abstract:Large resource cost is the design bottleneck of high-precision float-point FFT processor,a novel R2/22SDF reconfigurable architecture using shared-butterfly which employs single-port-based FIFO.Radix 2/22algorithm and pipeline architecture,which is suitable for float-point design,can reduce the multiplicative complexity and improve the multiplication efficiency.The FIFO memory using double-width single-port ram can avoid the larger area and power coat of dual-port ram.Two butterfly units can be merged by the proposed shared-butterfly architecture,which solves the low utilization factor problem of traditional single-path-delay-feedback architecture.The float-point design cost is efficiently reduced and the calculator utilization factor is improved,compared with the traditional pipeline method.
Keywords:fast fourier transform  reconfigurable float-point design  shared-butterfly  single-path-delay-feedback pipeline architecture
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