基于断言的验证方法在UART模块中的应用研究

介绍了一种易于实现的基于断言的验证(ABV)方法,即经过5个步骤在设计文件中插入断言,使仿真器在仿真过程中监视设计中的关键功能点.该方法在UART的寄存器传输级(RTL)模型功能验证中的应用,实验中使用SVA描述设计属性.实验证明,这一方法提高了设计的可观察性,适用于数字集成电路功能验证.

Research of Assertion-Based verification Method on UART

This paper presents an easy-approached assertion-based verification (ABV) method by embedding assertions in source codes to monitor key function spots of the design during simulation. This method is approached by five steps. As an application example, a case study of functional verification for a UART RTL model, using System Verilog Assertion (SVA) to describe the properties, is provided. The studied result shows that the new method is feasible and can be applied in the design and verification process to increase the observability of the design.