一种新的基于层次化模式实现的SOC时钟设计方法

通过对SOC传统时钟设计在层次化开发模式下遇到的新问题进行分析，提出了一种新的时钟设计方法．利用相位同步信号（Phase_sync）作为层次化模式中顶层（Top）和子设计（Sub--design）之间的桥梁，有效解决了顶层时序收敛时对子设计内部时序路径造成的影响．同时，规避了对时钟分频电路进行复位同步化处理，降低了物理设计时序收敛的难度．

New Method of SOC Clock Design Based on Hierarchical Mode

In this paper,the new problems of traditional clock design in the hierarchical mode were analyzed and a new method of clock design was proposed.A phase_sync signal was used as a bridge of the top and sub-design in this method.It effectively prevents the 'damage' to the internal timing of subchip caused by the top-level timing closure.At the same time,the application of this method avoids reset design of clock divider circuit and reduces the difficulty of back-end timing closure.