低功耗非全摆幅互补传输管加法器

文章提出了一种新型传输管全加器,该全加器采用互补传输管逻辑（Complementary Pass-Transistor Logic）实现.与现有的CPL全加器相比：该全加器具有面积、进位速度和功耗上的优势：并且提供了进位传播信号的输出,可以更简单的构成旁路进位加法器（Carry SkipAdder）.在此全加器基础上可以实现一种新型行波进位加法器（Ripple Carry Adder）,其内部进位信号处于非全摆幅状态,具有高速低功耗的特点.HSPICE模拟表明：对4位加法器而言,其速度接近CMOS提前进位加法器（Carry Look ahead Adder）,而功耗减小了61%.适用于高性能、低功耗的VLSI电路设计.

Low-Power Non-full Swing Complementary Pass-Transistor Logic Adder

This paper proposed a novel FA (Full Adder) cell, which is implemented by using CPL (Complementary Pass-transistor Logic) technology. Compared with conventional CPL FA: this FA is superior in area, carry propagation speed and power dissipation, and it also provides carry propagation signal which will help implement CSA (Carry Skip Adder) more easily. A new RCA (Ripple Carry Adder) based on this FA is fast and low-power because the internal carry signal is in non-full swing phase. HSPICE circuit simulation on 4bit adder shows: its speed is closed to CMOS CLA (Carry Look ahead Adder), but with 61% power reduced. It is suitable for high performance and low-power dissipation VLSI design.