UML到Verilog同态映射在SOC系统级建模上的应用

SOC设计变得日益复杂要求我们在更高层次抽象上分析和验证系统行为。更精细的系统级建模方法变得日趋重要。文章主要目标是阐述怎样使用统一建模语言UML来构建一个复杂SOC设计框架及抽象其各个模块间行为的交互，建立了一个UML到Verilog的同态映射。提出了一个基于同态映射的从UML模型子集自动导出相应可综合Verilog描述的算法，为UML模型对于建模硬件系统提供了形式化的语义，从而能够验证并综合UML模型，加快了SOC设计流程。

Homomorphic Mapping from UML to Verilog in SOC System-Level Modeling

The constantly increasing complexity of today's SOC design demands analysis and verification of system behavior on higher levels of abstraction. More elaborate system - level modeling techniques are more and more important. The main aim of this paper is to present how the Unified Modeling Language (UML) can be used in the construction of a framework of a complex SOC design and the abstraction of behavioral interactions among each function. A homomorphic mapping between UML metamodel and Verilog is constructed. A homomorphic based algorithm for automated deriving synthesizable Verilog specification is put forward. It enable us to verify and synthesize the UML models, so accelerates the flow of the SOC design.