基于130 nm CMOS工艺的5 Gbit/s 10:1并串转换芯片

介绍了一种基于GSMC 130 nm CMOS工艺的高速率低功耗10:1并串转换芯片。在核心并串转换部分,该芯片使用了多相结构和树型结构相结合的方式,在输入半速率时钟的条件下,实现了10路500 Mbit/s并行数据到1路5 Gbit/s串行数据的转换。全芯片完整后仿真结果显示,在工作电压(1.2±10%)V、温度-55~100℃、全工艺角条件下,该芯片均可正确完成10:1并串转换逻辑功能,并输出清晰干净的5 Gbit/s眼图。在典型条件下,芯片整体功耗为25.2 mW,输出电压摆幅可达到260 mV。

5 Gbit/s 10 to 1 Parallel-to-Serial Conversion Chip Based on 130 nm CMOS

This article describes a high-speed,low-power 10:1 parallel-to-serial conversion chip based on the GSMC 130 nm CMOS.In the core parallel-serial conversion part,the chip uses a combination of a multi-phase structure and a tree structure to realize conversion of 10 channels of 500 Mbit/s parallel data to 1 channel of 5 Gbit/s serial data under the condition of inputting a half rate clock.After the complete chip is completed,the simulation results show that the chip can correctly complete the 10:1 parallel-to-serial conversion logic function at a working voltage of(1.2±10%)V and a temperature of-55-100℃under full process angle,and the output is a clear 5 Gbit/s eye diagram.Under typical conditions,the overall power consumption of the chip is 25.2 mW,and the output voltage swing can reach 260 mV.