| 一种双核SoC调试系统的设计与验证 |
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| 引用本文： | 虞致国,魏敬和.一种双核SoC调试系统的设计与验证[J].电子与封装,2010,10(1):21-23,34. |
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| 作者姓名： | 虞致国 魏敬和 |
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| 作者单位： | 中国电子科技集团公司第58研究所,无锡,214035 |
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| 摘 要： | 调试系统的设计和验证是多核SoC设计中的重要环节。基于某双核SoC的设计,提出一个片上硬件调试构架,利用FPGA构建该调试系统的硬件验证平台。双核SoC调试系统验证平台利用System Verilog DPI,将RealView调试器、Keil C51及目标芯片的验证testbench集成在一起,实现了双核SoC调试系统的RTL级调试验证。利用该平台,在RTL仿真验证阶段可方便地对ARM和8051核构成的双核SoC进行调试,解决仿真中出现的问题,从而有效缩短设计周期,并提高验证效率。该双核SoC调试系统验证平台的实现对其他系统芯片设计具有一定的参考价值。
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| 关 键 词： | 双核 调试系统 SystemVerilog直接编程接口 虚拟验证平台 JTAG |
Design and Verification of Debug System for a Dual-core SoC |
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| YU Zhi-guo,WEI Jing-he.Design and Verification of Debug System for a Dual-core SoC[J].Electronics & Packaging,2010,10(1):21-23,34. |
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| Authors: | YU Zhi-guo WEI Jing-he |
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| Affiliation: | The 58th Research Institute of China Electronic Technology Group Corporation;Wuxi 214035;China |
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| Abstract: | The design and verification of debug system for a dual-core SoC is very important.Based on the design of a dual-core SoC,an on-chip design for debug architecture is proposed and a verification platform for a debug system based on SystemVerilog direct programming interface(DPI) is implemented.The platform integrates software debugger RealView and verification testbench for target device to debug the debug system of dual-core SoC when the design is in RTL-level phase.The efficiency of debug system verificatio... |
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| Keywords: | dual-core debug system system verilog DPI virtual verification platform JTAG |
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