| 0.6μm SOI NMOS器件ESD性能分析及应用 |
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| 引用本文： | 罗静,胡永强,周毅,邹巧云,陈嘉鹏.0.6μm SOI NMOS器件ESD性能分析及应用[J].电子与封装,2011,11(11):33-36,40. |
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| 作者姓名： | 罗静 胡永强 周毅 邹巧云 陈嘉鹏 |
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| 作者单位： | 中国电子科技集团公司第58研究所,江苏无锡,214035 |
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| 摘 要： | ESD设计是SOI电路设计技术的主要挑战之一,文章介绍了基于部分耗尽0.6μm SOI工艺所制备的常规SOI NMOS器件的ESD性能,以及采用改进方法后的SOI NMOS器件的优良ESD性能。通过采用100ns脉冲宽度的TLP设备对所设计的SOI NMOS器件的ESD性能进行分析,结果表明：SOI NMOS器件不适合...
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| 关 键 词： | 静电放电 SOINMOS ggNMOS gcNMOS |
0.6μm SOI NMOS ESD Performance Analysis and Application |
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| LUO Jing,HU Yong-qiang,ZHOU Yi,ZOU Qiao-yun,CHEN Jia-peng.0.6μm SOI NMOS ESD Performance Analysis and Application[J].Electronics & Packaging,2011,11(11):33-36,40. |
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| Authors: | LUO Jing HU Yong-qiang ZHOU Yi ZOU Qiao-yun CHEN Jia-peng |
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| Affiliation: | (China Electronic Technology Group Corporation No.58 Research Institute,Wuxi 214035,China) |
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| Abstract: | ESD design is one of major challenges for SOI circuit design.This paper introduces the ESD performance of SOI NMOS and updated SOI NMOS by process and design methods for a partially depleted 0.6μm SOI process.Through ESD performance analysis of SOI NMOS by 100ns pulse width TLP test system,we show that SOI NMOS is not suitable for main ESD protection structure directly in SOI circuit.But with updated process and design methods,SOI NMOS is suitable for main ESD protection structure in output buffer and VDD-to-VSS ESD of SOI circuit. |
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| Keywords: | ESD SOI NMOS ggNMOS gcNMOS |
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