一种应用于流水线ADC采样保持电路的设计

介绍了一种应用于12位、10MS/s流水线模数转换器前端的高性能采样保持（SH）电路的设计。该电路采用全差分电容翻转型结构及下极板采样技术,有效地减少噪声、功耗及电荷注入误差。采用一种改进的栅源电压恒定的自举开关,极大地减小电路的非线性失真。运算放大器为增益增强型折叠式共源共栅结构,能得到较高的带宽和直流增益。该采样保...

Design of Sample-and-hold Circuit for a Pipeline ADC

A high performance sample and hold（SH） circuit for use in the front end of a 12-bit 10MS/s Pipeline ADC is presented.The full differential capacitor flip-around architecture has been used to reduce both noise and power.To reduce the nonlinearity error cause by the sampling switch,a signal dependent clock bootstrapping system is used.A fully differential folded cascade operational amplifier is designed using a gain-boosted circuit to get high gain and wideband.It is implemented using 0.6μm BiCMOS process,and simulation results demonstrate that the S/H circuit consumes 11mW at 5V supply with a sampling rate of 10MHz.A 107.8dB spurious-free dynamic range（SFDR）,an 88.1dB signal and noise ratio（SNR）,and a-105.2dB total harmonic distortion（THD）are obtained.