SOI CMOS Implementation of a Multirate PSK Demodulator for Space Communications |
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Authors: | Mehmet Rasit Yuce Wentai Liu John Damiano Bhaskar Bharath Paul D Franzon Numan S Dogan |
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Affiliation: | Dept. of Electr. Eng. & Comput. Sci., Univ. of Newcastle, Callaghan, NSW; |
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Abstract: | A low-power phase-shift keying demodulator integrated circuit (IC) has been implemented using silicon-on-insulator CMOS technology for deep space and satellite applications. The demodulator employs double differential detection to increase its robustness to the Doppler shift caused by the movement of the space vehicle and sampling technique with 1-bit analog-to-digital converter (ADC) at the front to reduce the complexity and power dissipation. In particular, digital decimation is used after sampling to achieve a low power implementation of multirate transmission. Operating at ultra-high-frequency (435 MHz), the receiver system supports a wide range of data rates (0.1-100 Kbps). From test results, the power consumption of the demodulator circuit including the 1-bit ADC is below 1 mW for data rates up to 100 Kbps |
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