A 90-nm CMOS 1.8-V 2-Gb NAND flash memory for mass storage applications |
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Authors: | Lee J Sung-Soo Lee Oh-Suk Kwon Kyeong-Han Lee Dae-Seok Byeon In-Young Kim Kyoung-Hwa Lee Young-Ho Lim Byung-Soon Choi Jong-Sik Lee Wang-Chul Shin Jeong-Hyuk Choi Kang-Deog Suh |
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Affiliation: | Memory Div., Samsung Electron. Co. Ltd., Gyeonggi, South Korea; |
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Abstract: | A 1.8-V 2-Gb NAND flash memory has been successfully developed on a 90-nm CMOS STI process technology, resulting in a 141-mm/sup 2/ die size and a 0.044-/spl mu/m/sup 2/ effective cell. For the higher level integration, critical layers are patterned with KrF photolithography. The device has three notable differences from previous generations. 1) The cells are organized in a single (16K+512) column and 128K row array by adopting a one-sided row decoder in order to minimize the die size. 2) The bitline precharge level is set to 0.9 V in order to increase on-cell current. 3) During the program operations, the string select line, which connects the NAND cell strings to the bitlines, is biased with sub-V/sub CC/ in order to avoid program disturbance issues. |
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