基于CPLD／FPGA的AES算法混合流水实现

在加解密算法的硬件实现中,使用流水线结构可以显著地提高加密解密速度,但是由于这类结构并不适合于大多数的反馈模式,因而此类结构在当前密码学中的应用较少。为此,该文采用一种补偿手段,基于交叉CBC(Interleaved Cipher Block Chaining)模式,以混合流水结构成功地实现了AES(Advanced EncryptionStandard)的算法。该方案允许并行处理4个数据块(称为一次加密或解密),同时两次加密或解密之间还可实现部分并行。该方案在EP20k300EBC652-1(Ateral公司产品)上已得到成功验证。

The Hybrid Pipelining Implementation of AES in the Feedback Mode Based on CPLD/FPGA

Although using pipelining structure in the hardware implementation can generally provide higher throughput, the application of this structure in current cryptography is limited, because they are not suitable for most common feedback modes. This paper puts forward a design of the hybrid pipelining architecture of AES. By including in the AES standard interleaved modes of operation, the design successfully implements the algorithm, which operates in the CBC mode. In this design, four data blocks can be dealt with in parallel (called one-encryption or one-decryption), and at the same time two encryptions or decryptions can be partially overlapped. The design has been implemented on EP20k300EBC652-l device (Ateral).