ANT-on-YARDS: FPGA/MPU hybrid architecture for telecommunicationdata processing

This paper presents a novel system architecture that combines tightly coupled field programmable gate arrays (FPGA's) and a microprocessing unit (MPU) that we have developed. This system architecture comprises three main programmable devices which yield high flexibility. These devices are a reduced instruction set computer (RISC)-type MPU with memories, programmable interconnection devices, and FPGA's. This system supports various styles of coupling between the FPGA's and the MPU which makes several data processing operations more effective. Furthermore, we indicate the most suitable applications for the system. They are telecommunication data processes involving complex protocol operations and network control algorithms. In this paper, two applications of the system are given. One is for operation, administration, and management (OAM) cell processing on an asynchronous transfer mode (ATM) network. The other is a dynamic remote reconfiguration protocol that enables the functions of the transport data processing system to be updated or changed on-line