基于并行FIR滤波器结构的数字下变频

对宽带信号进行并行处理,可同时满足低功耗和实时性的要求,已成为目前宽带信号处理的研究热点。本文提出了一种可在FPGA中实现的并行快速FIR滤波器设计方法。该方法通过应用并行多相处理技术中的一种新型分布式处理算法,在滤波器结构上实现了多级级联的形式,增强了中频处理的灵活性和通用性,节省了硬件开销。仿真结果表明,该算法很好的解决了原始低通滤波器速度跟不上A/D采样率的问题,把采样率提高到了320MHz以上。同时该方法应用软件实现并行信号处理,避免了使用DDC专用芯片,具有较强的通用性,可以很好的移植到其他CPLD中。

Digital Down-Conversion Based on Parallel FIR Filter Architecture

Parallel processing to broadband signals can meet low power consumption and real-time requirements; it has become a research hotspot of broadband signal processing. A parallel fast finite impulse response （FIR） filter design method based on FPGA is presented. By using of a novel distributed processing algorithm for parallel multi-phase processing technology, multi-stage cascade in the filter structure is implemented, flexibility and versatility of intermediate frequency （IF） signal processing is improved, and cost of hardware gets reduced. Simulation results show that the algorithm is a good solution to solve problem that speed of original low-pass filters can not keep up with the A/D sampling rate, therefore sampling rate can be increased up to more than 320MHz. Additionally, parallel signal processing is implemented through software, therefore special chip for digital down-conversion （DDC） is eliminated ; the method has good universality, it can be easily applied in other complex programmable logic devices （CPLDs）.