| 一种任意抽取数字下变频器的设计 |
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| 引用本文： | 袁子乔,刘翔.一种任意抽取数字下变频器的设计[J].火控雷达技术,2013(3):66-69. |
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| 作者姓名： | 袁子乔 刘翔 |
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| 作者单位： | 西安电子工程研究所,西安710100 |
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| 摘 要： | 数字下变频（DDc）技术作为连接前端模数转换器件（ADC）与后端通用数字信号处理器件之间的纽带，在雷达信号处理中占据了核心地位。针对雷达不同模式下抽取率不同的情况，本文提出了一种任意抽取数字下变频芯片的设计，实现了不同抽取率时的乘法器资源复用，节约了乘法器资源，降低了系统功耗和系统的复杂度。该数字下变频芯片采用SMICO．13μm工艺进行综合仿真，综合结果满足指标要求。
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| 关 键 词： | 专用集成电路 Cordie 数字下变频 |
Design of an Arbitrary Decimation DDC |
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| Yuan Ziqiao,Liu Xiang.Design of an Arbitrary Decimation DDC[J].Fire Control Radar Technology,2013(3):66-69. |
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| Authors: | Yuan Ziqiao Liu Xiang |
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| Affiliation: | ( Xi ＇an Electronic Engineering Research Institute, Xi ＇an 710100) |
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| Abstract: | Digital down-conversion （DDC） plays a very important role in radar signal processing as a link between analog-to-digital converter （ADC） at the front-end and general digital signal processor at the back-end. To different decimation in different radar operate mode, design of an arbitrary decimation DDC application specific integrated circuit （ASIC） is provided for implementation of multiplexing of multiplier source, therefore multiplier source is saved and system power consumption and complexity are both reduced. Synthesized simulation to this DDC chip by using SMIC 0. 13 μm technology indicated that its performance can meet specification requirements. |
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| Keywords: | ASIC Cordic DDC |
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