一种全CMOS工艺吉比特以太网串并-并串转换电路

本文介绍了一种单片集成的吉比特以太网串并－并串转换电路。在芯片中，模拟锁相环产生1．25GHz高速时钟（当芯片用于光纤网络，时钟速率就为1．06GHz)，同时一个10到1多路选择器完成并行数据到串行的转换。在接收端，差分输入信号依次经过均衡电路、双端－单端转换电路转换成数字信号。同时，数据和时钟提取电路提取出时钟，并将数据重新同步。最后，串并转换电路完成串行－并行转换和字节同步。实验芯片采用0．35μmSPTM CMOS工艺，芯片面积为1．92mm^2，在最高输入输出数据波特率条件下的功耗为900mW。

A fully integrated CMOS Gigabit Ethernet serialize & de-serialize transceiver chip

A 1.25GHz fully integrated CMOS Gigabit Ethernet SERDES chip is described in this paper. It uses a PLL to generate the 1.25GHz (1.06GHz while used in fiber channel) clock and a 10 to 1 Frame mux to serially output the 8B/10B encoded parallel data. In the receiver section, a clock and data recovery circuit extracts the 1.25GHz (1.06GHz) clock from the data which has been changed from differential two-ended to one-ended signal by an equalizer and dual to single circuit. Frame demux then converts the realigned data to parallel data. The byte synchronization is also fabricated in the chip. This fully integrated transceiver is fabricated by 0.35mm SPTM CMOS technology, 1.92 square millimeters in area and 900mW at the highest baud rate data pattern is achieved.