新型浮栅MOS单管动态比较器设计

提出一种新型浮栅MOS单管动态比较器的电路结构。以浮栅MOS单管为核心,根据浮栅电荷的保持特性,在时钟控制下,两个电压分时地输入浮栅MOS管从而引起浮栅电位变化,相对变化后的浮栅电位决定着比较管的再通断,使预充电的输出电容与源极电容重新分配电荷,通过输出电容上电压是否发生变化来反映比较结果。单管比较避免差分对管由于工艺偏差所引起的输入失调问题,而且以浮栅偏置抵消MOS管的阈值。采用charted0.35μmCMOS工艺设计电路,面积约为0.003mm2,经前、后仿真和流片测试,结果表明,电路功能正确。并且在3.3V电源电压下、比较时间为0.4μs时,平均功耗为2.8mW。

Design of a Novel Comparator Using Floating-gate MOS Single Transistor

A novel circuit structure of comparator is presented.The core of comparator design is a floating-gate MOS single transistor.According to the charge maintains characteristic in floating gate,the reference voltage and input voltage change floating-gate potential orderly in different time under the CLK control to drive the MOS transistor being on or off,and to redistribute pre-charge from the output-capacitor to source-capacitor.So the voltage on output capacitor is changed that the voltage comparison result can be obtained.Simultaneously,the threshold is counteracted by floating-gate bias.The result is correct by pre-simulation and post-simulation.The comparator is realized in Charted 0.35 μm CMOS standard process.The chip area is 0.003 mm2.Test shows that the power consumption,in 0.4 μs,is about 2.8 mW at a supply voltage of 3.3 V.