Fast and gate-count efficient arithmetic logic unit |
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Authors: | Yong Surk Lee Joh P Jae Hee You Kyu Tae Park |
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Affiliation: | Dept. of Electron. Eng., Yonsei Univ., Seoul; |
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Abstract: | A CMOS arithmetic logic unit is presented with a minimum number of transistors and high speed arithmetic operations. Multiple carry chain adders and a novel 1 bit adder, are used in a carry select adder. The carry chain adder has a high degree of shared gates with a low propagation delay |
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