Optimization methodology for the width of the fixed-point decimal multiplier

With the progress of design and fabrication in the semiconductor area, the chip scale and complexity are raised rapidly, and low-power design becomes a very important topic. This paper presents a low-power optimization methodology for the width of the fixed-point decimal multiplier, describes its principle and implementation, and verifies its optimization result by the FPGA test. On the methodological level, its optimization object is the width of the adders, which are inside the synthesized multiplier. On the circuit level, it resolves the problem of introducing the logic in the optimized system, which exists in the present low power design. The methodology has good performance in optimizing the system including large-scale multipliers, such as DSP, digital filter, etc.