一种有限扫描操作测试压缩方法

针对集成电路测试时间长，导致测试费用高的问题，提出了一种基于有限扫描操作的扫描电路静态测试压缩方法．利用有限扫描操作代替全扫描操作，用有限扫描操作合并测试对，通过减少移位操作次数减少测试时间．同时，将启发式方法用于限制候选测试对数量，给候选测试对进行排序，降低计算复杂度，加速压缩过程．基准电路实验结果表明，相同故障覆盖率下，本方法所需平均测试时间仅为典型方法的50％左右．

Novel approach to test compaction based on limited scan operation

According to the problem of the significant increasing testing cost of VLSI caused by the significant increase in testing time, this paper proposes a novel approach to test compaction for scan circuits that use limited scan operations instead of full scan operations between test pairs. This leads to very aggressive compaction on the test application time cost under the same fault coverage. The experimental result of benchmark circuits shows that the test application time cost of the proposed method is about 50％ that of the conventional methods.