1.5bit substage circuit for charge domain pipelined ADCs

A 1.5bit sub-stage circuit based on bucket-brigade devices (BBD) for high speed charge domain pipelined ADCs is presented to solve the problem that the performances of high-speed, high-resolution ADCs rely on the opamps with large gain-bandwidth production, which results in large power consumption. Charge transfer and residue charge calculation are realized with a boosted charge transfer (BCT) circuit in the proposed 1.5bit sub-stage, and therefore, the high-performance opamps in traditional pipelined ADCs are eliminated and the power consumption can be reduced remarkably. Based on the proposed 1.5bit sub-stage circuit, a 10bit 250MS/s charge domain pipelined ADC is designed in 0.18μm CMOS technology. Measurement results under a sampling frequency of 250MHz and an input sinusoidal frequency of 9.9MHz show that the ADC achieves a spurious free dynamic range (SFDR) of 64.4dB and a signal-to-noise-and-distortion ration(SNDR) of 56.9dB, with power consumption of only 45mW.