Feedback tuning algorithm for fast-locking all-digital phase-locked loops

An adaptable feedback tuning algorithm based on the analyses of various phase detection mechanisms and filter architectures is presented to shorten the locking time of all-digital phase-locked loops (ADPLLs). The algorithm divides the entire locking processes into coarse tuning, first fine tuning and second fine tuning processes corresponding to control codes of coarse, first and second fine stages in the digitally controlled oscillator (DCO). An appropriate filter architecture is chosen in each process while adaptive factors are tunable according to the value of the frequency error. A portable fast-locking fractional-N ADPLL based on the proposed algorithm is fabricated by 180nm CMOS technology. Measurement shows that the average locking time is only 6.4μs, that is, 128 reference cycles with a 20MHz clock. The locking time is reduced by the algorithm effectively.