用于快速锁定全数字锁相环的反馈调节算法

为降低全数字锁相环的锁定时间，在分析了不同相位检测机制和滤波器结构的基础上提出了自适应的反馈调节算法．该算法将锁定过程分为粗调、一级精调、二级精调三部分，分别对应数控振荡器的三级控制码，在不同的锁定过程中使用合适的滤波器结构且可根据频率差的大小自适应调节参数．基于所提算法，在180nm CMOS工艺下实现了一款可移植的快速锁定的小数全数字锁相环．测试结果表明:平均锁定时间仅为6.4μs，相当于128个参考时钟周期(20MHz)，该算法有效地缩短了锁定时间．

Feedback tuning algorithm for fast-locking all-digital phase-locked loops

An adaptable feedback tuning algorithm based on the analyses of various phase detection mechanisms and filter architectures is presented to shorten the locking time of all-digital phase-locked loops (ADPLLs). The algorithm divides the entire locking processes into coarse tuning, first fine tuning and second fine tuning processes corresponding to control codes of coarse, first and second fine stages in the digitally controlled oscillator (DCO). An appropriate filter architecture is chosen in each process while adaptive factors are tunable according to the value of the frequency error. A portable fast-locking fractional-N ADPLL based on the proposed algorithm is fabricated by 180nm CMOS technology. Measurement shows that the average locking time is only 6.4μs, that is, 128 reference cycles with a 20MHz clock. The locking time is reduced by the algorithm effectively.