| Design of systolic BN circuits in Galois fields based on quaternary logic |
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| 作者姓名： | 吴海霞 屈晓楠 何易瀚 郑瑞沣 仲顺安 |
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| 作者单位： | School of Information and Electronics, Beijing Institute of Technology, Beijing 100081, China;School of Information and Electronics, Beijing Institute of Technology, Beijing 100081, China;School of Information and Electronics, Beijing Institute of Technology, Beijing 100081, China;School of Information and Electronics, Beijing Institute of Technology, Beijing 100081, China;School of Information and Electronics, Beijing Institute of Technology, Beijing 100081, China |
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| 基金项目： | Supported by Science Foundation of Beijing Institute of Technology (20120542012) |
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| 摘 要： | The BNoperation is known as an efficient basic operation in Galois fields GF(2k),and various algorithms and implementations using binary logic signals have already been proposed.In order to reduce the circuit complexity and long latency of BNoperations,a novel algorithm and its systolic architecture are proposed based on multiple-value logic(MVL).In the very large scale integration(VLSI)realization,a kind of multiple-valued current-mode(MVCM)circuit structure is presented and in which the combination of dynamic source-coupled logic(SCL)and different-pair circuits(DPCs)is employed to improve the switching speed and reduce the power dissipation.The performance is evaluated by HSPICE simulation with 0.18μm CMOS technology.The transistor numbers and the delay are superior to corresponding binary CMOS implementation.The combination of MVCM circuits and relevant algorithms based on MVL seems to be potential solution for high performance arithmetic operationsin Galois fields GF(2k).
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| 关 键 词： | multiple-valued logic BN operation Galois fields |
| 收稿时间： | 2012/12/10 0:00:00 |
Design of systolic BN circuits in Galois fields based on quaternary logic |
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| WU Hai-xi,QU Xiao-nan,HE Yi-han,ZHENG Rui-feng and ZHONG Shun-an.Design of systolic BN circuits in Galois fields based on quaternary logic[J].Journal of Beijing Institute of Technology,2014,23(1):58-62. |
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| Authors: | WU Hai-xi QU Xiao-nan HE Yi-han ZHENG Rui-feng and ZHONG Shun-an |
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| Affiliation: | School of Information and Electronics, Beijing Institute of Technology, Beijing 100081, China;School of Information and Electronics, Beijing Institute of Technology, Beijing 100081, China;School of Information and Electronics, Beijing Institute of Technology, Beijing 100081, China;School of Information and Electronics, Beijing Institute of Technology, Beijing 100081, China;School of Information and Electronics, Beijing Institute of Technology, Beijing 100081, China |
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| Abstract: | The BN operation is known as an efficient basic operation in Galois fields GF (2k), and various algorithms and implementations using binary logic signals have already been proposed. In order to reduce the circuit complexity and long latency of BN operations, a novel algorithm and its systolic architecture are proposed based on multiple-value logic (MVL). In the very large scale integration (VLSI) realization, a kind of multiple-valued current-mode (MVCM) circuit structure is presented and in which the combination of dynamic source-coupled logic (SCL) and different-pair circuits (DPCs) is employed to improve the switching speed and reduce the power dissipation. The performance is evaluated by HSPICE simulation with 0.18 μm CMOS technology. The transistor numbers and the delay are superior to corresponding binary CMOS implementation. The combination of MVCM circuits and relevant algorithms based on MVL seems to be potential solution for high performance arithmetic operationsin Galois fields GF(2k). |
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| Keywords: | multiple-valued logic BN operation Galois fields |
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