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一种双游程编码的测试数据压缩方案
引用本文:商进,张礼勇.一种双游程编码的测试数据压缩方案[J].哈尔滨理工大学学报,2010,15(4):19-22.
作者姓名:商进  张礼勇
作者单位:1. 哈尔滨理工大学,测控技术与通信工程学院,黑龙江,哈尔滨,150080;黑龙江工程学院,电子工程系,黑龙江,哈尔滨,150050
2. 哈尔滨理工大学,测控技术与通信工程学院,黑龙江,哈尔滨,150080
基金项目:黑龙江省教育厅科学技术研究项目 
摘    要:SOC芯片测试中一个主要的挑战就是处理大量的测试数据.为了减少芯片测试中的测试数据,提出了一种双游程的编码方案,采用变长到变长的编码方式对0游程和1游程进行编码.该算法在编码时同时考虑0游程和1游程,大大减少了测试数据中短游程的数量,同时文中给出了一种基于有限状态机的解压缩算法的实现方案.理论分析和实验结果证明该方案具有高压缩率、硬件实现简单等特点.

关 键 词:测试数据压缩  解压  双游程编码

Scheme of Test Data Compression Based on Dual-run-length Code
SHANG Jin,ZHANG Li-yong.Scheme of Test Data Compression Based on Dual-run-length Code[J].Journal of Harbin University of Science and Technology,2010,15(4):19-22.
Authors:SHANG Jin  ZHANG Li-yong
Affiliation:1.School of Measure-control Technology and Communication Engineering,Harbin University of Science and Technology,Harbin 150080,China;2.Department of Electronic Engineering,Heilongjiang Institute of Technology,Harbin 150050,China)
Abstract:One of the major challenges in testing a system-on-a-chip is dealing with a large volume of test data.To reduce the volume of test data,dual-run-length code is proposed in this paper,a variable-to-variable run-length code based on encoding both runs of 0s and 1s.Both runs of 0s and 1s are considered in this method so as to reduce the number of short runs,and the circuit structure of decoder with FSM is proposed.Theoretical analysis and experimental results show that this schemes is a very efficient compression method.
Keywords:test data compression  decompression  dual-run-length code
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