Impact of platinum contamination on ferroelectric memories |
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| Authors: | Hocine Boubekeur Thomas Mikolajick Nicolas Nagel Christine Dehm Werner Pamler Anton Bauer |
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| Affiliation: | 1. Infineon Technologies, Memory Products , Balanstrasse 73, 81541, Munich, Germany;2. Infineon Technologies, Corporate Research , Otto-Hahn-Ring 6, 81730, Munich, Germany;3. Fraunhofer Institute of Integrated Circuit, IIS-B , Schottkystrasse 10, 91058, Erlangen, Germany |
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| Abstract: | Abstract The impact of platinum contamination on the breakdown properties of gate oxide is reported. Wafers were intentionally contaminated with 1×1013 to 4×1014 at/cm2 Pt after a 7.5 nm gate oxide growth, 300 nm poly-silicon deposition and subsequent phosphorus doping. Breakdown characteristics were evaluated using a voltage ramp method. The current-voltage curves of MOS capacitors show very few low field breakdown events, and the main field breakdown occurs at 12 MV/cm. If compared to clean wafers, platinum does not increase the defect density seriously. It is found from the E-Ramp results that platinum contamination up to 4×1014 at/cm2 does not have a pronounced effect on the gate oxide integrity if the contamination occurs after front-end-of-line processing of device fabrication. |
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| Keywords: | Platinum Metal contamination Gettering Gate Oxide Integrity E-ramp. |
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