组合电路可测试性技术的研究

随着集成电路设计规模的不断增大,在芯片中特别是系统芯片SOC(system on a chip)中组合电路的可测试性设计方法变得越来越重要.本文采用内建自测试技术对组合电路进行可测试性设计,详细分析了组合电路内建自测试的实现原理.通过将测试生成及响应分析逻辑置入电路内部,提高了电路的可控制性和可观察性,从而可使该电路的测试和诊断快速而有效.最后对8位行波进位加法器的内建自测试设计过程进行了详细分析,并通过MAX pluslI将其实现.

Research on the design for test of Combinatorial Circuit

With the growth of the scale of integrated circuits,the design for test for combinatorial circuit in the chip and particularly in the SOC is becoming more and more important.The paper presented the method based on built-in self-test(BIST) for the design for test.The principle of combinatorial circuit built-in self-test was analyzed in detail,which putting test pattern generation and response analysis logic into the circuit to enhance the controllability and observability of circuits,and made the test and diagnosis of combinatorial circuit quick and effective.At last,the BIST design of 8-bit ripple carry adder was analyzed in detail and was implemented by MAX plusII.