层次型结构片上网络测试方法研究

使用HDL硬件描述语言建模了在FPGA芯片中可综合实现的二维网状片上网络,在此基础上建立了片上网络测试平台。提出了一种新颖的基于全扫描和逻辑内建自测试的层次型结构片上网络测试方法,论述了层次型结构和非层次型结构SoC芯片测试方法的差异,给出了与IEEEStd.1500标准兼容的测试壳设计,测试响应特征分析使用空间和时间数据压缩技术。实验结果显示本文所提出测试方法能有效地减少测试时间和测试数据量,从而降低了整体测试成本。该方法适用于不同类型的片上网络。

Research on test strategy for hierarchical network-on-chips interconnection infrastructure

2D mesh topological NoC test platform described VHDL is modeled, and a novel test strategy for the hi-erarchical NoC interconnect infrastructure is proposed based on full scan, logic BIST and an IEEE Std. 1500-compliant test wrapper. The differences between the test method of hierarchical and non-hierarchical SoCs is discussed, and a space and time data compaction scheme used in test response analysis is described. The experimental results show that a good tradeoff of area overhead, test data volume, and te...