| 基于FPGA的64 kbit/s通信误码生成仪 |
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| 引用本文： | 尹成群,杨贵,陈俊莉.基于FPGA的64 kbit/s通信误码生成仪[J].电力系统通信,2006,27(8):66-69. |
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| 作者姓名： | 尹成群 杨贵 陈俊莉 |
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| 作者单位： | 1. 华北电力大学,电子与通信工程学院,河北,保定,071003
2. 许继昌南通信公司,河南,许昌,461000 |
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| 摘 要： | 介绍了利用FPGA实现64 kbit/s通信误码生成仪的具体实现方法,即为减轻CPU的工作负担,利用FPGA和SDRAM芯片IS61LV5128实现64 kbit/s信号的时延、在64 kbit/s信号中添加随机误码、连续误码的实现方法,利用FPGA实现从信号中提取时钟的锁相环电路的设计方法。利用ARM7的数据处理能力和FPGA并行处理能力相结合,适用于实时性要求高的场合,是一种实时信号处理新的实现方法的探索。
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| 关 键 词： | 现场可编程逻辑门阵列 锁相环 误码 |
| 文章编号： | 1005-7641(2006)08-0066-04 |
| 修稿时间： | 2006年2月28日 |
FPGA based the error code generator of 64 kbit/s |
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| YIN Cheng-qun,YANG Gui,CHEN Jun-li.FPGA based the error code generator of 64 kbit/s[J].Telecommunications for Electric Power System,2006,27(8):66-69. |
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| Authors: | YIN Cheng-qun YANG Gui CHEN Jun-li |
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| Abstract: | Introduced the concrete realization method of 64 kbit/s Error Code Generator using FPGA.In order to reduce the CPU working load introduced the realization method of 64 kbit/s signal time delay using FPGA and SDRAM IS61LV5128,the realization method of adding the random error code in the 64 kbit/s signal and continuous error code in detail.And introduced the phase-lock link circuit design method of using FPGA to pick-up clock signal from the communication signals.By unifying the ARM7 data-handling capacity and the FPGA parallel processing ability,this method is suitable for real-time operating,it is one kind of new realization method of real-time signal processing. |
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| Keywords: | Field Programmable Gate Array(FPGA) Phase Locked Loop(PLL) bit error code |
| 本文献已被 CNKI 维普 万方数据 等数据库收录！ |
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