实现相位和频率检测解耦的快速锁相环

同步旋转坐标锁相环(SRF-PLL)及其改进型锁相环的相位与频率紧密耦合,电压相位发生突变而频率不变的情况下,检测得到的频率会经历一个暂态过程,导致频率检测的不准确。为此,在准一阶锁相环(QT1-PLL)结构基础上,增设解耦单元,提出改进型准一阶锁相环(MT1-PLL),实现相位与频率检测的解耦。为提高MT1-PLL对不对称、谐波等的抗干扰能力,将级联延迟信号消除法(CDSC)滤波与数学运算滤波结合成前置滤波模块,提取基波正序电压。该前置滤波模块能够滤除2次谐波,且整个滤波过程耗时仅为0.635个周期。同时,考虑了电网频率偏移、信号采样频率的影响,采用误差前馈的方法补偿它们在滤波模块造成的相位误差。最后,在PSCAD/EMTDC中设置各种工况,仿真验证了MT1-PLL、滤波模块以及相位误差消除方法的有效性。

Fast Phase-locked Loop to Realize Decoupled Detection of Phase and Frequency

Detection of phase and frequency by synchronous reference frame phase-locked loop(SRF-PLL)and its improved versions are closely coupled. If the voltage with an unvaried frequency has a step change in phase angle, the detected frequency will suffer a transient process, causing errors to the detection of frequency. Thus, based on the structure of quasi-type-1 phase-locked loop(QT1-PLL), a modified quasi-type-1 phase-locked loop(MT1-PLL)is proposed with a decoupled unit, which is able to achieve decoupled detection of phase and frequency. In order to improve the ability of MT1-PLL to reject unbalance, harmonics, etc. , cascaded delayed signal cancellation(CDSC)is combined with a proposed mathematical filter, forming a pre-loop filtering module to extract fundamental positive sequence voltage. The module features the elimination of 2nd harmonics, and a fast filter process takes only 0. 635 cycles. Meanwhile, the phase errors in the module caused by deviations of grid frequency, and sampling frequency are also considered, which are compensated by an error feedforward method. Finally, simulations are conducted in PSCAD/EMTDC under various operation conditions to verify the effectiveness of MT1-PLL, filtering module and cancellation method of phase error.