An efficient small‐delay faults simulator based on critical path tracing

Testing for small‐delay defects (SDDs) has become an important component of integrated circuit testing. In this paper, an efficient small‐delay fault simulator, a hybrid method combining forward serial simulation and backward critical path tracing simulation for SDDs is proposed, which aims to determine the coverage of small‐delay defects for a given test set fast and accurately. In our proposed method, a unit delay model is employed, and reconvergent sensitization as well as hazard‐based detection is considered. Signal waveforms are expressed by bitmap data forms. In addition to providing an accurate result for fault simulation, the proposed simulator can well assist test generation. Experimental results demonstrate that the proposed simulator can further accelerate the simulation by one or two orders of magnitude compared with previous works. Copyright © 2014 John Wiley & Sons, Ltd.