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Design and performance study of phase‐locked loop using fractional‐order loop filter |
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| Authors: | Madhab Chandra Tripathy Debasmita Mondal Karabi Biswas Siddhartha Sen |
| Affiliation: | 1. Department of Electrical Engineering, Indian Institute of Technology Kharagpur, Kharagpur, India;2. Department of Biosciences and Bioengineering, Indian Institute of Technology Bombay, Mumbai, India |
| Abstract: | The present work reports the realization of an analog fractional‐order phase‐locked loop (FPLL) using a fractional capacitor. The expressions for bandwidth, capture range, and lock range of the FPLL have been derived analytically and then compared with the experimental observations using LM565 IC. It has been observed that bandwidth and capture range can be extended by using FPLL. It has also been found that FPLL can provide faster response and lower phase error at the time of switching compared to its integer‐order counterpart. Copyright © 2014 John Wiley & Sons, Ltd. |
| Keywords: | fractional‐order PLL (FPLL) fractional‐order loop filter (FLF) fractional‐order voltage controlled oscillator (FVCO) constant phase angle capture range lock range fractional capacitor |