| 基于SOC技术设计可复用的异步串行通信接口IP核 |
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| 引用本文： | 黄万伟,邵高平.基于SOC技术设计可复用的异步串行通信接口IP核[J].微计算机信息,2005,21(4):132-133,100. |
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| 作者姓名： | 黄万伟 邵高平 |
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| 作者单位： | 450002,郑州解放军信息工程大学,信息工程学院,郑州市1001信箱860分箱电子线路 |
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| 摘 要： | 基于SOC(system on chip)技术，利用VHDL语言设计开发具有奇偶校验功能、数据位和波特率可调的通用异步串行通信接口IP核。该IP核内置异步接收和发送模块，可直接提供给其它SOC系统设计者使用，减少SOC系统设计的工作量。
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| 关 键 词： | SOC VHDL 奇偶校验 波特率可调 |
| 文章编号： | 1008-0570(2005)04-0132-02 |
Design of Adopted Asynchronous Communication IP Core by means of SOC Technology |
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| Huang Wanwei,Shao Gaoping.Design of Adopted Asynchronous Communication IP Core by means of SOC Technology[J].Control & Automation,2005,21(4):132-133,100. |
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| Authors: | Huang Wanwei Shao Gaoping |
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| Abstract: | By means of SOC technology, the UART IP core is designed by VHDL language. The UART core comprises transmit and receive unit, supporting even or odd parity, controllable baud rate and serial data format. If necessary, the IP core can be adopted by other engineers immediately with no difficulty, reducing the work of SOC designing. |
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| Keywords: | SOC VHDL even or odd parity controllable baud rate |
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