| 一种改进的全数字锁相环设计 |
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| 引用本文： | 李肃刚,杨志家. 一种改进的全数字锁相环设计[J]. 微计算机信息, 2005, 0(15) |
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| 作者姓名： | 李肃刚 杨志家 |
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| 作者单位： | 辽宁沈阳中国科学院沈阳自动化研究所，辽宁沈阳中国科学院沈阳自动化研究所 110016 100039 北京中国科学院研究生院，110016 |
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| 基金项目： | 中国科学院知识创新工程重大项目编号:(KGCX-XW-15) |
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| 摘 要： | 本文在介绍了经典全数字锁相环(all digital PLL,AD-PLL)的基础上,提出了具有捕获锁定未知输入信号频率功能的ADPLL,使用方便,应用广泛。本文详尽的描述了系统的工作原理和关键部件的设计,通过计算机进行了仿真验证,并在可编程逻辑器件(FPGA)中予以实现。
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| 关 键 词： | 全数字锁相环(ADPLL) 鉴频器 异或门鉴相器(XOR-PD) 鉴频鉴相器(PFD) |
An Improved All Digital Phase-locked Loop Design |
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| Li,Sug-ang Yang,Zhijia Li,Sugang. An Improved All Digital Phase-locked Loop Design[J]. Control & Automation, 2005, 0(15) |
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| Authors: | Li Sug-ang Yang Zhijia Li Sugang |
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| Affiliation: | (Shenyang Institute of Automation,Chinese Acade-my of Sciences,Liaoning Shenyang,110016) Li,Sug-ang Yang,Zhijia(Graduate School of the Chinese Academy of Sci-ences,Beijing,100039) Li,Sugang |
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| Abstract: | This paper describes the theory and the developingstate of the All Digital Phase-Locked Loop (ADPLL) firstly, andpresents a new type of ADPLL, which can be applied under theenvironment of different and unknown signal frequencies. It alsointroduces the principle of the system and the implementation ofthe key parts of the design. Finally, it gives the simulation re-sults in PC and the implementation in FPGA. |
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| Keywords: | All Digital PhaseLocked Loop(ADPLL) Fre-quency Detector XOR Phase Detector(XORPD) Phase-Frequency Detector(PFD) |
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