| 单芯片可重构数字接收机的研究 |
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| 引用本文： | 马涛,陈娟,单洪. 单芯片可重构数字接收机的研究[J]. 微计算机信息, 2006, 22(23): 151-153 |
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| 作者姓名： | 马涛 陈娟 单洪 |
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| 作者单位： | 230037,合肥,电子工程学院 |
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| 摘 要： | 本文从系统的小型化和可重构性出发,利用可编程系统芯片(SOPC)技术,对单芯片可重构数字接收机的实现进行了研究,给出了具体的实现方案。在此基础上,利用系统工具DSPBuilder给出了QPSK解调功能模块的FPGA仿真与硬件验证。
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| 关 键 词： | 数字接收机 |
| 文章编号： | 1008-0570(2006)08-2-0151-03 |
| 修稿时间： | 2005-12-26 |
Study of the Reconfigurable Digital Receiver on a Chip |
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| Ma,Tao,Chen,Juan,Shan,Hong. Study of the Reconfigurable Digital Receiver on a Chip[J]. Control & Automation, 2006, 22(23): 151-153 |
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| Authors: | Ma Tao Chen Juan Shan Hong |
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| Abstract: | From the Miniaturized and reconfigurable system point of view, the realization of reconfigurable digital receiver on a chip is studied by use of SOPC technology, and the special project of the realization is given in this paper. On this basis, the FPGA emu- lation and hardware validation of the function block of QPSK demodulation is given by the system tool of DSP Builder. |
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| Keywords: | SOPC FPGA |
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