基于时钟树机制的超高速数字锁相放大系统

在超高速数字锁相系统中，虽然可以采用时间交替并行模数转换（Analog-to-digital converter, ADC）结构解决采样速率和采样精度的矛盾，但系统极易受各通道采样时钟抖动的影响。在分析采样时钟抖动与采样有效位数及动态范围关系的基础上，设计了一种基于时钟树机制的并联ADC交替采样结构的超高速数字锁相放大系统。实验结果表明，在相同的测试条件下，该系统比国外主流厂商的商用锁相放大器信噪比提高了约17.5 dB。

Ultra-high Speed Digital Phase-Locked Amplifier System Based on Clock Tree Mechanism

In the ultra-high speed digital phase-locked amplifier (PLA) system, the trade-off between sampling rate and sampling accuracy can be solved by using the conventional time-interleaved parallel analog-to-digital converter (ADC) structure. However, this system is very vulnerable to the impact of sampling clock jitter in each channel. Based on the analysis of the relationship between sampling clock jitter and effective sampling digits and dynamic range, a high-speed digital phase-locked amplifier system is realized by using the parallel ADC alternating sampling structure based on clock tree mechanism. Experimental results show that under the same test conditions, the signal-to-noise ratio of this system is increased by about 17.5 dB compared with that of commercial PLA manufactured by foreign mainstream manufacturers.