基于RISC-V处理器的固件更新系统设计

为简化嵌入式开发人员更新RISC-V处理器固件的操作流程，提出了一种易操作、高效且稳定的固件更新系统设计方法，包括BootROM引导流程设计和在应用中编程（in-application programming，IAP）设计。在BootROM引导流程设计中，通过启动参数再配置的方法，可使此引导流程兼容多种启动模式，如SRAM启动、主内存启动。在IAP设计中，处理器先通过通用异步收发传输器（universal asynchronous receiver/transmitter，UART）接收从上位机发送过来的新固件，该固件采用Ymodem协议发送，再通过串行外设接口（serial peripheral interface，SPI）进行片外Flash的重新烧写，以完成对系统固件的更新，同时，为保证接收新固件的可靠性，加入了循环冗余校验（cyclic redundancy check，CRC）算法。在现场可编程门阵列（field programmable gate array，FPGA）上对该系统进行了多次测试，均完成了对系统固件的更新，验证了该设计的可行性与稳定性。

Design of Firmware Update System Based on RISC-V Processor

In order to simplify the operating process of embedded developers to update the RISC-V processor firmware, an easy-to-operate, efficient and flexible firmware update system design method is proposed, including the BootROM boot design and the in-application programming（IAP） design. In the BootROM boot design, the boot parameter reconfiguration method can make the boot process compatible with multiple boot modes such as the SRAM boot and main memory boot. In the IAP design, the processor first receives the new firmware sent from the host computer through the universal asynchronous receiver/transmitter（UART） by using the Ymodem protocol, and then the off-chip Flash is reprogrammed through the serial peripheral interface（SPI） to complete the system firmware update. Meanwhile, a cyclic redundancy check（CRC） algorithm is designed to ensure the reliability of received new firmware. Finally, the system firmware update is successfully realized in multiple experiments performed on field programmable gate array（FPGA）, thus the feasibility and stability of the design are verified.