SPARC平台模拟器源码级调试系统的研究与实现

软件模拟器采用软件思想模拟真实硬件工作情况,作为嵌入式系统研究的基础研发工具,被广泛应用于体系结构设计调优、软硬件协同设计领域。研究提出一种在SPARC指令集模拟器平台上实现源码级调试系统的方法,一方面该方法使用SPARC交叉调试器对运行于SPARC指令集模拟器上的应用程序进行源码级调试,有效避免了单独实现源码级调试器所带来的调试信息解析困难、可靠性难以验证的弊端;另一方面提出了在集成开发环境下源码级调试系统的高效集成机制,有效解决了进程间切换延时开销大、界面僵死等问题,为SPARC平台嵌入式系统开发人员提供了一种支持图形化界面的高可靠性源码级调试系统。通过具体实现分析,对整个调试系统进行了性能评估。

Research and implementation of source-level debugging system on SPARC platform simulator

As a basic research tool for embedded systems, simulator is widely used in architecture design and hardware/software codesign. It uses software idea to simulate the behavior of hardware. This paper proposes a method to implement a source-level debugging system on a SPARC instruction set simulator. On the one hand, the system uses an existing SPARC cross debugger to reduce the development cycle and increase the reliability. Compared to reimplementing a source-level debugger, the method over-comes the difficulties of debug information extracting and reliable verification. On the other hand, the paper proposes a mecha-nism which binds the source-level debugging system to Integrated Development Environment. This mechanism reduces the run-time overhead of context switch and prevents screen blocking. In summary, the system provides a high reliability of source-level debugging interface for the developers of SPARC embedded systems. The correctness and performance of entire debugging system are evaluated on SparcSim simulator.