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一种可测性分析的新方法
引用本文:邢军.一种可测性分析的新方法[J].计算机工程与应用,2009,45(28):86-88.
作者姓名:邢军
作者单位:牡丹江师范学院 计算机科学与技术系,黑龙江 牡丹江 157012
摘    要:提出一种基于时序泰勒展开图(TTED)的VLSI高层可测性分析(TA)新方法,以时序泰勒展开图(TTED)为关键敏化路径建模,建立起确定性和概率性故障的统一表示模型。利用符号变量获取线路的敏感性,并且考虑电路的单敏化和多敏化情况,进行电路的可测性计算和分析,取得了较好的效果,实验证实了该方法的有效性。

关 键 词:超大规模集成电路(VLSI)  可测性  敏化方程  时序泰勒展开图
收稿时间:2009-4-14
修稿时间:2009-6-15  

New method of testability analysis
XING Jun.New method of testability analysis[J].Computer Engineering and Applications,2009,45(28):86-88.
Authors:XING Jun
Institution:Department of Computer Science,Mudanjiang Teachers Colleges,Mudanjiang,Heilongjiang 157012,China
Abstract:This paper proposes a VLSI high-level testability analysis(TA) new approach HLTA-TTED based on Timed Taylor Expansion Diagram(TTED),which models the critical sensitization path with TTED and establishes a unique representation model of certainty and probability failure.The line’s sensitization is obtained by using the symbolic variable.Considering the case of single sensitization and multi-sensitization of the circuit,this paper computes and analyzes the testability of the circuit.A good result is obtained at last,the experiment confirms the approach’s effectiveness.
Keywords:Very Large Scale Integrated circuits(VLSI)  testability  sensitization equation  Timed Taylor Expansion Diagram(TTED)
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