| 高速连续数据流记录系统中并行处理接口的研究 |
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| 引用本文： | 郭文秀,董永贵,孙照焱,马骋,熊剑平,贾惠波.高速连续数据流记录系统中并行处理接口的研究[J].计算机工程与应用,2002,38(6):67-69,100. |
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| 作者姓名： | 郭文秀 董永贵 孙照焱 马骋 熊剑平 贾惠波 |
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| 作者单位： | 清华大学精密仪器与机械学系,北京,100084 |
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| 基金项目： | 973国家重点基础研究发展规划项目(编号:G19990330) |
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| 摘 要： | 为了解决高速数据流的连续记录/读取与存储介质速度慢之间的矛盾,文中用FPGA设计了基于RAID结构的并行处理接口,实现了高速数据的分割降速、合并/恢复、纠错重构,解决了高速数据流连续存储中的I/O瓶颈问题。并行处理接口采用了流水线的设计方式及动态的逻辑配置,使得系统性能得到很大的优化,解决了高速数据处理中的延迟、数据错误、工作时序不同步等问题。并行处理接口最终在实验系统中实现了对高达160MB/S连续实时数据流的处理。
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| 关 键 词： | FPGA 流水线设计 动态配置 高速数据流 |
| 文章编号： | 1002-8331-(2002)06-0067-03 |
An Parallel Processing Interface for Recording the High-speed Continuous Data Stream |
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| Guo Wenxiu Dong Yonggui,Sun Zhaoyan Ma,Cheng Xiong Jianping Jia Huibo.An Parallel Processing Interface for Recording the High-speed Continuous Data Stream[J].Computer Engineering and Applications,2002,38(6):67-69,100. |
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| Authors: | Guo Wenxiu Dong Yonggui Sun Zhaoyan Ma Cheng Xiong Jianping Jia Huibo |
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| Abstract: | To solve the conflict between high-speed recording /reading of continuous data stream and low-speed storage device,a parallel processing interface based on RAID architecture is developed.The interface is implemented on an FP-GA chip.It has3main functions:dividing high-speed continuous data stream to several low-speed data streams for fur-ther parallel processing,combining /restoring separate data streams to one continuous data steam,correcting the error da-ta stream.Pipelining technology and dynamic logic configuration method is used in the design,which improves the total interface performance and eliminates many problems in processing high-speed data stream such as delay,misdata and asynchronous operation.An experimental system is constructed for evaluating the performance of the interface.Initial re-sults show that the interface can be used for processing high-speed continuous data stream at speed up to160MB/S. |
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| Keywords: | FPGA Pipelining Dynamic configuration High-speed data stream |
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