| Abstract: | Logic simulation is used extensively in the design of digital systems for the purpose of studying the behaviour of circuits under various conditions and for verifying the required performance of circuits. There is considerable interest in methods which reduce the simulation time during the design process. In this paper, we investigate how this can be achieved by simulating the action of logic circuits using a network of loosely coupled processors. Circuits modelled as directed graphs comprising clocked sequential components and (unclocked) arbitrary combinational logic gates can be partitioned into separate tasks each consisting of a sequential component with an associated network of combinational components. We present cost functions for evaluating a task subject to probabilistic assumptions about the functioning of the circuits. The circuit evaluation method used in the simulation process is significant. We apply lazy evaluation, a demand-driven evaluation strategy in which signals in the circuit are evaluated on a ‘need to do' basis, resulting in a considerable saving in circuit simulation time. We achieve distributed logic simulation using a network of workstations and show from experimental results that by using such a configuration, we essentially obtain a single computation engine which can be used to obtain speedups in circuit simulation when compared with uniprocessor simulation systems. Interprocess communications between tasks on different workstations proceed via remote procedure calls while local communications between tasks take place via shared memory. The method of partitioning used in the circuit model ensures that communications between tasks take place only at defined times in the simulation sequence. |
