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A metaprogrammed C++ framework for hardware/software component integration and communication
Affiliation:1. Aab Cardiovascular Research Institute, Department of Medicine, University of Rochester School of Medicine and Dentistry, New York, USA;2. Functional Genomics and Systems Biology Group, IBM T.J. Watson Research Center, New York, USA;3. Cardiology Division, Department of Medicine, University of Rochester School of Medicine and Dentistry, New York, USA;1. Department of Biomedical Engineering, Cleveland Clinic, Cleveland, OH, USA;2. Center for Neurological Restoration, Cleveland Clinic, Cleveland, OH, USA;3. Cleveland FES Center, L. Stokes Cleveland VA Medical Center, Cleveland, OH, USA;4. Department of Preventive Cardiology, Cleveland Clinic, Cleveland, OH, USA;5. Jacobs University, Bremen, Germany;6. Iowa State University, Ames, IA, USA
Abstract:With the ever growing complexity of System-on-Chip design, a considerable effort has been made to introduce higher levels of abstraction and to integrate high-level synthesis solutions to the design flow. In such design flows, a uniform communication interface is needed to enable high-level implementations of SoC components regardless of whether they are compiled as software running on a processor or synthesized to dedicated hardware IPs. This paper addresses this issue and proposes a component communication framework that defines an object-oriented remote call mechanism which allows transparent communication across hardware/software boundaries. The proposed framework relies on C++ static metaprogramming techniques to efficiently abstract communication between components implemented using high-level C++. We also define a portability layer that enables the migration of designs throughout different hardware platforms, operating systems, and tools. We assessed the performance and area footprint of our communication infrastructure through the implementation of a voice processing pipeline on top of a Network-on-Chip based architecture. Our results, when compared to previous related works with the same set of capabilities, show that our mechanisms yield small overhead in terms of software memory (up to 64% smaller), FPGA resources (up to 40% smaller), and hardware/software communication latency (up to 51% smaller).
Keywords:System-on-Chip  System-level design  High-level synthesis  HW/SW co-design  HW/SW communication
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