Real-Time neural signal decoding on heterogeneous MPSocs based on VLIW ASIPs |
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| Affiliation: | 1. Dipartimento Ingegneria Elettrica ed Elettronica, Università degli Studi di Cagliari, Cagliari, 09123, Italy;2. PolComIng – Gruppo Ingegneria dell’Informazione, Università degli Studi di Sassari, Sassari, 07100, Italy;1. State Key Laboratory of ISN, Xidian University, Xi''an, China;2. The University of Otago, Otago, New Zealand;3. Institute of Microelectronics, Xidian University, Xi''an, China;4. School of Computer Science and Technology, Xidian University, Xi''an, China;1. Department of Electronics and Communications Engineering, Tampere University of Technology, Tampere, Finland;2. Nokia Solutions and Networks, Espoo, Finland;1. School of Microelectronics, Shanghai Jiao Tong University, 800 Dongchuan Road,Shanghai 200240, P.R. China;2. Department of Electrical and Computer Engineering, National University of Singapore, 21 Lower Kent Ridge Road, Singapore;3. Department of Computer Science, Pace University, 1 Pace Plaza, Manhattan, New York City, NY, 10038, USA;4. Shanghai Key Laboratory of Data Science, Fudan University, 825 Zhangheng Road, Shanghai 201203, P.R. China;5. PLA Information Engineering University, P.R. China;6. School of Computing, National University of Singapore, Singapore;1. Beijing Advanced Innovation Center for Imaging Technology, Beijing, China;2. College of Information Engineering, Capital Normal University, Beijing, China;3. College of Computer Science, Chongqing University, Chongqing, China;4. Department of Computing, The Hong Kong Polytechnic University, Hong Kong |
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| Abstract: | An important research problem, at the basis of the development of embedded systems for neuroprosthetic applications, is the development of algorithms and platforms able to extract the patient’s motion intention by decoding the information encoded in neural signals. At the state of the art, no portable and reliable integrated solutions implementing such a decoding task have been identified. To this aim, in this paper, we investigate the possibility of using the MPSoC paradigm in this application domain. We perform a design space exploration that compares different custom MPSoC embedded architectures, implementing two versions of a on-line neural signal decoding algorithm, respectively targeting decoding of single and multiple acquisition channels. Each considered design points features a different application configuration, with a specific partitioning and mapping of parallel software tasks, executed on customized VLIW ASIP processing cores. Experimental results, obtained by means of FPGA-based prototyping and post-floorplanning power evaluation on a 40nm technology library, assess the performance and hardware-related costs of the considered configurations. The reported power figures demonstrate the usability of the MPSoC paradigm within the processing of bio-electrical signals and show the benefits achievable by the exploitation of the instruction-level parallelism within tasks. |
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