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基于FPGA的数字Costas锁相环路的设计
引用本文:刘殿敏,李科杰.基于FPGA的数字Costas锁相环路的设计[J].小型微型计算机系统,2005,26(5):877-880.
作者姓名:刘殿敏  李科杰
作者单位:北京理工大学,机电工程学院,北京,100081
摘    要:介绍了应用EDA技术设计嵌入式全数字Costas锁相环路的方法.建立了连续域环路线性模型,给出环路方程,并利用连续域和离散的变换关系,即Laplace变换和Z变换的关系,由连续域环路的线性相位模型推导出了离散域环路的线性相位模型,由此来讨论二阶Costas环路在离散域实现方法,讨论了离散域中环路滤波器的传递函数及实现,讨论了DCO的离散设计方法及实现,并采用从逻辑电路的顶层到底层以及模块化的设计思想,用VHDL缟程语言,通过逻辑综合和仿真,可缟程逻辑器件FPGA予以实现.

关 键 词:EDA技术  VHDL语言  全数字二阶COSTAS锁相环路  片上系统(SOC)  FPGA
文章编号:1000-1220(2005)05-0877-04

Design of Digital Costas Phase-locked Loop Based on FPGA
LIU Dian-min,LI Ke-jie.Design of Digital Costas Phase-locked Loop Based on FPGA[J].Mini-micro Systems,2005,26(5):877-880.
Authors:LIU Dian-min  LI Ke-jie
Abstract:Presented the designing method of digital Costas phase-locked loop(PLL) with EDA technology. Linear model was set up in continuous time domain and gives loop equation. Utilizing the relation of Laplace transform and Z transform, linear phase model of second order discrete time domain Costas loop circuits was deduced from phase continuous time domain model . The implementation method of discrete Costas loop was researched. Loop filter was discussed in discrete time domain. The discrete time domain implementation method of DCO was discussed. Logical circuit of the digital second order Costas loop was implemented in FPGA chip with VHDL. VHDL program was synthesized with synplify tool. The function of design was simulated with applied software tool modesim.
Keywords:EDA technology  VHDL  digital second order costas phase-locked loop  system on chip  FPGA  
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