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VHDL编译型事件驱动模拟算法
引用本文:吴清平,刘明业.VHDL编译型事件驱动模拟算法[J].计算机学报,2002,25(1):30-35.
作者姓名:吴清平  刘明业
作者单位:北京理工大学ASIC研究所,北京,100081
摘    要:VHDL模拟器在VLSI高层设计验证中起着重要的作用,设计正确性的快速有效检索对加快整个设计流程至关重要,模拟算法从根本上决定了模拟验证的效率,是构造高效模拟器的关键。文中讨论了VHDL的各种不同模拟算法,提出了将编译型实现算法与事件驱动调度算法结合的模拟算法,并提出了将VHDL设计源描述转化为等价C++代码再编译为机器目标代码的模拟算法实现方法。此算法结合了事件驱动调度算法的模拟元件数少和编译型实现算法执行速度高的优点,并巧妙利用了面向对象的多态性特点,具有速度快、直观和易于扩弃的优点。文章最后给出了试验结果,进一步说明了算法的效率和优点。

关 键 词:VHDL  事件驱动  编译型  模拟算法  超大规模集成电路
修稿时间:2000年11月17

Algorithm for Compiled Event-Driven VHDL Simulation
WU Qing\|Ping\ LIU Ming\|Ye.Algorithm for Compiled Event-Driven VHDL Simulation[J].Chinese Journal of Computers,2002,25(1):30-35.
Authors:WU Qing\|Ping\ LIU Ming\|Ye
Abstract:VHDL Simulator plays a key role in the verification of VLSI high\|level design, and the fast and efficient check of the design validity speeds up the design flow significantly. The simulation algorithm determinate the efficiency of a simulator, and it is the key factor in constructing an efficient simulator. This paper discusses the classification of VHDL simulation algorithms first. The simulation algorithm consists of two parts: schedule algorithm and implementation algorithm. Schedule algorithm is either oblivious or event\|driven. In oblivious algorithm, each component is evaluated at each time point, producing a new design state for the next time point. In event\|driven algorithm, changes in design state are recorded, only those components that might cause a change in design state during a given time point are simulated. Implementation algorithm is either interpretive or compiled. In interpretive algorithm, a data structure that represents the design is constructed, and a central scheduler iterates over simulation time, calling procedures that evaluate the design component. Compiled algorithm produces a straight\|line program with all data addressed directly by the code. Compiled algorithm works more efficiently because of reducing the overhead of traversing the design structures. Most published implementations of compiled simulation used the oblivious schedule algorithm. This paper presents an algorithm for compiled event\|driven VHDL simulation. To implement this algorithm, a simulation schedule kernel is programmed and compiled into a C library first, which can be used to manage and schedule the events occuring during the simulation. Then we translate VHDL sources of design into C codes, which finally can be compiled into an executable simulation file. To make the precompiled simulation kernel and the codes translated from VHDL source, we smartly apply the encapsulation, inheritance and polymorphism characteristic of Object\|Oriented technique into the algorithm, which make this algorithm more graceful and efficient. Also, we put forward a method of translating VHDL codes into C codes that is also Object\|Oriented, and it works well with the VHDL simulation algorithm. The algorithm presented in this paper combines the merit of compiled implementation algorithm and event\|driven algorithm, and has characteristics of high performance and easy expansion. This algorithm has been used in the author's compiled VHDL simulator. In the last part of this paper, we verify the performance and efficiency of the algorithm by some experiment data derived from author's prototype simulator.
Keywords:VHDL  event\|driven  compiled  simulation algorithm  simulator  
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