协作式全局指令调度与寄存器分配

指令级并行是现代高性能代理器的重要特征，对于发挥这类处理器所具有的并行处理能力来说，编译器有至关重要的影响。文中讨论指令级并行编译中的核心问题－全局指令调度与 器分配，并以作者为一种新型的显式并行体系结构微处理器的编译系统为背景，介绍了此类编译器后端设计中面临的指令调度与寄存器分配的时序问题，以及为解决这一问题而提出了的一种协作式全局指令调度与寄存器分配方法。

Cooperating Global Instruction Scheduling and Instant Register Allocation

Instruction Level Parallelism (ILP) is an important characteristic of current high performance processor. Compiler has critical impact on how to make full use of the strong parallel processing ability of this kind of processor. With the background of developing an ILP compiler for a VLIW like processor, this paper discusses the kernel problem of ILP compilation global instruction scheduling and register allocation, introduces the phase ordering problem faced the design of the back end of this compiler, and presents the cooperated global instruction scheduling and register allocation method as a solution.