芯片功耗与工艺参数变化:下一代集成电路设计的两大挑战

目前Intel、AMD、IBM等国际著名厂商均将其集成电路生产工艺全面转入65nm制程,对于以高性能为目标的高端芯片设计,受到了来自成本、设计与测试复杂性等方面的诸多挑战.文中主要论述了其中两个重要而具体的挑战:高功耗和日益显著的工艺参数变化(process variation).首先分析了纳米工艺下芯片功耗的组成、高功耗的诸多危害和目前主要的低功耗设计方法;然后分析了工艺参数变化的组成,较大工艺参数变化对电路设计的影响以及电路性能分析、功耗分析和低功耗设计的统计式算法;最后结合笔者的研究工作,简单地对下一代集成电路设计的相关研究热点进行预测.

Power Consumption and Process Variations: Two Challenges to Design of Next-generation ICs

Famous IC vendors including Intel,AMD,IBM have scaled their IC technologies into 65nm.High-end IC design aiming at high performance has faced many challenges from cost,com- plexities of design and test,and etc.This paper describes two important and detail challenges: High power consumption and rampant process variations(PV)in nanometer regime.This paper includes following three parts.First,it consecutively describes components of IC power con- sumption,several negative influences originated from high power,and mainstream low-power de- sign methods.Second,it consecutively describes components of process variations,their negative influences on IC design,and statistical algorithm that studies about static delay analysis(STA), power analysis,and low-power design.Last,combining with the authors' own research,this pa- per simply presents hot research topics on these two challenges of next-generation IC design.